1. Field of the Invention
The present invention relates to adaptive calibration of capacitor values in a successive approximation analog-to-digital converter having a radix weighted multi-capacitor charge redistribution digital-to-analog converter (CRDAC), and more particularly to adaptive calibration of the capacitor values in the CRDAC, and methods and systems for establishment and selection of bit testing sequences including companion bits for test bits used in sar processing systems, or the use of bit testing sequences in capacitor arrays relatively ratioed for radix less than two sar processing, or companion bit methods and systems for calibration and conversion with digital-to-analog converter (dac) elements in an analog-to-digital (a/d) converter.
2. Description of the Related Art
One attempt to design a successive approximation adaptive calibration architecture with feedback is described in David R. Welland""s U.S. Pat. No. 4,709,225 (granted in 1987). Binary weighting after wafer fabrication is set forth in the patent according to the Welland approach, which includes adjusting an array of capacitors scaled according to a radix 2 (i.e., binary) function, resulting in non-overlap.
Related art U.S. Pat. No. 4,336,526 granted to Basil Weir describes successive approximation analog-to-digital (A/D) conversion using a radix less than two weighted digital-to-analog converter (DAC) in a feedback loop using a comparator and a successive approximation register (SAR) logic circuit to solve the binary non-overlap problem. While Weir mentions vaguely the use of more than one bit, he offers no suggestion of particular bit sequences. He suggests no bit patterns. A proposed conversion operation produces a digital output representative of an unknown analog input. A DAC accepts a digital word comprising a sequence of series bits, to produce a corresponding analog voltage value. An impedance network is described including capacitors, for example, which have sequential capacitance values which are a function of radix less than two. Costly and complicated switching circuits precisely represent accurate series weights in such an impedance network. A first analog cancellation voltage is produced in the DAC with a selected most significant bit (MSB) capacitance. The first analog cancellation voltage is input to a comparator to set-off a received analog voltage which is to be converted into digital form by SAR conversion. If the first analog cancellation voltage from the MSB is insufficient to cancel out the received analog voltage under conversion, as evidenced by the sign of the output value from the comparator, then the tested MSB is kept. Unfortunately, Weir does not show or suggest adaptive calibration.
In a binary sequence network, the most significant binary capacitance in a selected impedance network of n capacitors slightly exceeds the sum of the remaining totality of less significant capacitances. Accordingly, if by virtue of noise or some other ancillary effect, a MSB is erroneously kept, then not even summing all the contributions from the remaining less significant bits will result in an approximation which has a cumulative value greater than the voltage of the capacitor associated with the most significant bit. In other words, the use of radix less than two for successive approximation according to the prior art is technically disadvantageous, because for radix less than two, there is no recovery from an erroneous (e.g., noise-induced) approximation with a particular most significant value bit, because the sum of the less significant bit capacitances or voltage figures does not reach either singly or cumulatively to the magnitude of the single erroneously kept voltage or capacitance level. Simply stated, with a radix less than two series, there is no redundancy which permits alternative expressions of particular voltage or capacitance levels.
One technical problem in successive approximation in a redundant system under noisy conditions is that a more significant, i.e., greater magnitude, element is erroneously kept as a result of the noise. Because the actual voltage being tested has thus been overapproximated, all remaining lesser magnitude test elements will fail and not be kept, but still the overapproximation cannot be corrected, because the remaining course of successive approximation will only query whether to increase the estimate, which is already excessive, by increasingly diminished test values. Unfortunately, there are no negative test values which can chip away at or reduce the excessive magnitude element already kept. Accordingly, it is desirable to avoid erroneous, noise-induced selection of excessively large test elements.
According to the present invention, a system for selection and use of bit testing sequences in radix less than two A/D SAR converters, includes control logic circuitry including a linear feedback shift register, a companion bit generator, and a successive approximation register connected to said linear feedback shift register and said companion bit generator. The system further includes a multiplexer connected to the control logic circuitry and calibration logic circuitry connected to the multiplexer. Additionally, the system includes a memory system connected to the calibration logic circuitry and an accumulator system connected to the memory system and the calibration logic circuitry.
According to one embodiment of the present invention, bit testing sequences are established for successive approximation testing in an overlapping decision space in which more than one set of capacitors can represent a particular in-range voltage value, whereby redundancy of bit representation of measured analog values is established. According to the present invention, a particular selected test element is accompanied by at least a single next-in-order test element having a predetermined number element separation from the preceding test element. A subsequent next-in-order test element will have the same predetermined number separation from the adjacent test element. The overlapping decision space is accessed by successive approximation with test sequences having the property of including a plurality of test bits including a first, most significant test bit followed by any predetermined number of zeros, followed by a next most significant companion test bit followed by any number of zeros in turn followed by a next-most significant companion test bit.
According to the present invention, imprecise DAC elements are selected and arranged in succession within a redundant, radix less than two envelope. According to one embodiment, the imprecise DAC elements substantially follow the contour of the envelope of a selected radix value which is less than two. Further according to the present invention, digital calibration of DAC elements in an ADC is adaptive, i.e., responsive to the precise actual element values. The DAC element values are not adjusted electrically or mechanically to follow a predetermined scheme or curve. Instead, the actual DAC element values are accommodated and used for self-calibration in adaptive fashion depending on their actual physical values. Digital weights representing the actual DAC element values are stored in memory digitally.
Further, according to one embodiment of the present invention, the successive approximation with test elements (e.g., without limitation resistive or capacitive) is accompanied with one or more companion bit elements, to provide a bias against keeping excessively large test values during calibration and/or conversion operation for an analog-to-digital converter which includes a digital-to-analog converter.
According to one embodiment of the present invention, adaptive calibration of a charge redistribution digital-to-analog converter includes producing a set of sampling bits to connect sampling components such as capacitors or resistors to a selected reference voltage. Different sets of sampling bits are used to cover a selected calibration range, with the sampling sets being predetermined, fixed, random, or pseudo-random. Each set of sampling bits produces a corresponding sampled value. The sampled value is approximated with successive balancing values produced with corresponding sets of balancing bits. An analog residue is produced from the difference between the sampled and balancing values. Digital weights are generated corresponding to the sampling and balancing bits. A digital residue is determined from the difference between the sampling and balancing digital weights. The charge redistribution digital-to-analog converter includes a set of multi-valued components which can redundantly approximate particular sampled values. According to one embodiment of the present invention, the set of components includes capacitors which can be organized into subsets of capacitance values which can redundantly approximate desired capacitance values within a predetermined range.
According to the present invention, adaptive calibration is accomplished without an external impulse by a non-binary companion bit charge redistribution digital-to-analog SAR converter. Companion bits are selected lower significance bits used with associated test bits to choose particular capacitors during SAR processing and having a predetermined magnitude relationship with the test bits. Conversion of SAR capacitors according to the present invention includes balancing a sampled charge with a group of capacitors having capacitance values scaled according to a radix less-than-two function and including companion bit capacitors.